This invention relates generally to computer processor operation, and more particularly to providing a method, system, and computer program product for reducing cache memory pollution.
In order to reduce or avoid the time delay (or “latency”) of accessing data stored in the main memory of a computer, modem computer processors include a cache memory (or “cache”) that stores recently accessed data so that it can be quickly accessed again by the processor. Data that is stored in a cache can be quickly accessed by a processor without the need to access the main memory (or “memory”), thereby increasing the performance of the processor and the computer overall. However, if the data needed by the processor does not exist (i.e., is not currently stored) in the cache, which is known as a “miss”, then the processor is subject to the latency of accessing the memory for the needed data. A miss can also occur in cache memory designs that include a low level cache (e.g., an “L1 cache”) and one or more higher level caches (e.g., an “L2 cache”, “L3 cache”, etc.) when the data needed by the processor does not exist in the L1 cache and the processor has to access a higher level cache, which also results in latency.
To reduce or avoid the latency of accessing data from the main memory or a higher level cache when there is a miss, data is often preloaded (or “prefetched”) into the cache (or the L1 cache in the case of a multiple level cache) before it is needed by the processor. Thus, when the needed data is referenced by the processor, the resulting latency (or “miss penalty”) is avoided if the data was prefetched or reduced if a prefetch of the data from the memory or a higher level cache is already in progress. However, prefetches of data are typically speculative, so it is not assured that prefetched data will be used by the processor. Since a cache memory (whether L1, L2, etc) is usually a fraction of the size of a main memory, a limited amount of data can be stored in the cache, and existing data is removed (or evicted) from the cache to provide space for newly prefetched data when the cache is full. Therefore, prefetched data that is not used by the processor can negatively affect performance by causing useful data to be evicted from the cache (or the L1 cache in a multi-level cache design), thereby requiring the processor to access the memory (or a higher level cache) to reference the useful data when it is needed. This eviction of useful data as a result of prefetching unneeded data is known as cache pollution, and it is desirable to reduce cache pollution.